-
sent/topic/sm8550/upstream/bwmon-v2d600b2a4 · ·
dt-bindings: interconnect: qcom-bwmon: document SM8550 compatibles Document the compatibles used to describe the Bandwidth Monitors present on the SM8550 platform. A BWMON v4 IP monitors the CPU bandwidth, and a v5 does the LLCC bandwidth monitoring. This is described by adding "llcc" and "cpu" into the compatible strings to differentiate the BWMON IPs. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Georgi Djakov <djakov@kernel.org> To: Rob Herring <robh+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- Changes in v2: - Reworded commit message - Added Reviewed-by from Krzysztof - Link to v1: https://lore.kernel.org/r/20221114-narmstrong-sm8550-upstream-bwmon-v1-0-b6dd08927f35@linaro.org --- .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index be29e0b80995..00b635662697 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -26,8 +26,13 @@ properties: - enum: - qcom,sc7280-cpu-bwmon - qcom,sdm845-bwmon + - qcom,sm8550-cpu-bwmon - const: qcom,msm8998-bwmon - const: qcom,msm8998-bwmon # BWMON v4 + - items: + - enum: + - qcom,sm8550-llcc-bwmon + - const: qcom,sc7280-llcc-bwmon - const: qcom,sc7280-llcc-bwmon # BWMON v5 - const: qcom,sdm845-llcc-bwmon # BWMON v5 --- base-commit: 3aec1f3082a7f388d04a1fa1a351aa25fd6335f0 change-id: 20221114-narmstrong-sm8550-upstream-bwmon-a7c6227fab6d Best regards, -
sent/topic/sm8550/upstream/spmi-v21770ab07 · ·
qcom: add support for SPMI PMICs found on SM8550 platforms The SM8550 based platforms sports a bunch of new PMICs: - pm8550 - pm8550b - pm8550ve - pm8550vs - pmk8550 - pmr735d - pm8010 With GPIO support on: - pm8550 - pm8550b - pm8550ve - pm8550vs - pmk8550 - pmr735d This documents bindings for those SPMI PMIC and adds compatible in the PMIC pinctrl driver for GPIO support. To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Lee Jones <lee@kernel.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Stephen Boyd <sboyd@kernel.org> To: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-gpio@vger.kernel.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v2: - Squashed patch 3 & 2 into 1, added Reviewed-by from Krzysztof - Squashed patch 5 into 4, added Reviewed-by from Krzysztof - Squashed patch 7 into 6, added Reviewed-by from Konrad - Link to v1: https://lore.kernel.org/r/20221114-narmstrong-sm8550-upstream-spmi-v1-0-6338a2b4b241@linaro.org --- Neil Armstrong (3): dt-bindings: mfd: qcom,spmi-pmic: document pm8550, pm8550b, pm8550ve, pm8550vs, pmk8550, pm8010 & pmr735d dt-bindings: pinctrl: qcom,pmic-gpio: document pm8550, pm8550b, pm8550ve, pm8550vs, pmk8550 & pmr735d pinctrl: qcom: spmi-gpio: add support for pm8550 & pmr735d gpio control .../devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 7 +++++++ .../devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 18 ++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 6 ++++++ 3 files changed, 31 insertions(+) --- base-commit: 8274e19d9db1019f8fac39cf46da6680513fd5d3 change-id: 20221114-narmstrong-sm8550-upstream-spmi-d2c999ec5dc1 Best regards, -
sent/mdm9615-pinctrl-yaml-v5c5233c59 · ·
arm: qcom: mdm9615: second round of bindings and DT fixes This is a second round of bindings & DT fixes for the MDM9615 platform. This second round focuses on less trivial changes like pinctrl & regulators bindings, the remaining work will mainly be fixing the qcom,kpss-timer/qcom,msm-timer situation and add bindings for qcom,lcc-mdm9615, qcom,kpss-gcc & swir,mangoh-iotport-spi. Dependencies: None To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Liam Girdwood <lgirdwood@gmail.com> To: Mark Brown <broonie@kernel.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Lee Jones <lee@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v5: - Fixed bindings invalid id after rename - Fixed invalid ref path to qcom,rpm-regulator.yaml from qcom,rpm.yaml bindings - Link to v4: https://lore.kernel.org/r/20221005-mdm9615-pinctrl-yaml-v4-0-463523919c19@linaro.org Changes in v4: - Removed applied patches - Removed "-ipc" from bindings file name and removed IPC from title & description - Added the review tags from v3 after file renaming & title/description change, after Lee's acceptation - Link to v3: https://lore.kernel.org/r/20221005-mdm9615-pinctrl-yaml-v3-0-e5e045644971@linaro.org Changes in v3: - Path 1: Removed from serie because applied - Path 2: None - Path 3: Added reviewed-by tag - Path 4: Fixed dt-schema title and added unevaluatedProperties - Path 5: Various schema fixes, uses same naming as other dt-schema for qcom regulators - New patch added changing regulators names of msm8660 to conform to bindings - Link to v2: https://lore.kernel.org/r/20221005-mdm9615-pinctrl-yaml-v2-0-639fe67a04be@linaro.org Changes in v2: - Rebased on v6.1-rc1 - Patch 1: Fixed bindings and aligned with Krysztof's series - Patch 2: Rewrote patch title and added reviewed-by tag - Patch 3: Added reviewed-by tag - Patch 4: Moved to end, added support for (regulators|-regulators) sudnode - Patch 5: Fixed schema description and added missing unevaluatedProperties in patternProperties - Patch 6: Dropped & squashed with patch 4 - Link to v1: https://lore.kernel.org/r/20221005-mdm9615-pinctrl-yaml-v1-0-0cbc006e2a30@linaro.org --- Neil Armstrong (2): dt-bindings: regulators: convert non-smd RPM Regulators bindings to dt-schema dt-bindings: soc: qcom: convert non-smd RPM bindings to dt-schema Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 283 --------------------- .../bindings/regulator/qcom,rpm-regulator.yaml | 128 ++++++++++ .../devicetree/bindings/soc/qcom/qcom,rpm.yaml | 101 ++++++++ 3 files changed, 229 insertions(+), 283 deletions(-) --- base-commit: 19d64985796125c5e3820c3db995c5df6d13d6dc change-id: 20221005-mdm9615-pinctrl-yaml-13f5c18a4d3a Best regards, -
sent/topic/sm8550/upstream/dts-qce-v1c3515914 · ·
arm64: dts: qcom: sm8550: add QCrypto nodes Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Depends on: - QCE new socs support [1] - SM8550 QCE bindings [2] - SM8550 base DT [3] To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org [1] https://lore.kernel.org/all/20220920114051.1116441-1-bhupesh.sharma@linaro.org/ [2] https://lore.kernel.org/all/20221114-narmstrong-sm8550-upstream-qce-v1-0-31b489d5690a@linaro.org/ [3] https://lore.kernel.org/all/20221116103146.2556846-1-abel.vesa@linaro.org/ --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 07ba709ca35f..a490b705ce5c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1372,6 +1372,30 @@ mmss_noc: interconnect@1780000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + + crypto: crypto@1de0000 { + compatible = "qcom,sm8550-qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; --- base-commit: a237afe452d9079aa024e465642b4cde0a04c7ff change-id: 20221115-topic-sm8550-upstream-dts-qce-7f4fe79e0375 Best regards, -
sent/topic/sm8550/upstream/dts-i2c-master-hub-v11db6a852 · ·
arm64: dts: qcom: sm8550: add I2C Master Hub nodes Add the I2C Master Hub wrapper and I2C serial engines nodes. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Depends on: - I2C Master Hub bindings [1] - SM8550 base DT [2] To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org [1] https://lore.kernel.org/all/20221114-narmstrong-sm8550-upstream-i2c-master-hub-v1-0-64449106a148@linaro.org/ [2] https://lore.kernel.org/all/20221116103146.2556846-1-abel.vesa@linaro.org/ --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 181 +++++++++++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 07ba709ca35f..e10ec73d66ab 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -985,6 +985,187 @@ spi15: spi@89c000 { }; }; + i2c_master_hub_0: geniqup@9c0000 { + compatible = "qcom,geni-se-i2c-master-hub"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clock-names = "s-ahb"; + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c_hub_0: i2c@980000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00980000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c0_data_clk>; + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_1: i2c@984000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00984000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c1_data_clk>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_2: i2c@988000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00988000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c2_data_clk>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_3: i2c@98c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c3_data_clk>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_4: i2c@990000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00990000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c4_data_clk>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_5: i2c@994000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c5_data_clk>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_6: i2c@998000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c6_data_clk>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_7: i2c@99c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c7_data_clk>; + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_8: i2c@9a0000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x009a0000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c8_data_clk>; + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_9: i2c@9a4000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x009a4000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c9_data_clk>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; --- base-commit: a237afe452d9079aa024e465642b4cde0a04c7ff change-id: 20221115-topic-sm8550-upstream-dts-gpi-qup-ba5e8fdb77a5 Best regards, -
sent/topic/sm8550/upstream/dts-remoteproc-v10e86c234 · ·
arm64: dts: qcom: Add ADSP, CDSP & MDSS support to SM8550 and MTP board This adds support for the aDSP, cDSP and MPSS Subsystems found in the SM8550 SoC. The aDSP, cDSP and MPSS needs: - smp2p support nodes to get event back from the subsystems - remoteproc nodes with glink-edge subnodes providing all needed resources to start and run the subsystems In addition, the MPSS Subsystem needs a rmtfs_mem dedicated memory zone. Finally the firmwares file paths are added in the MTP board DT. For the MPSS to successfully start the MPSS DSM driver [3] will be needed. This patchset depends on: - bindings changes at [1] - base SM8550 DT at [2] To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> [1] https://lore.kernel.org/all/20221114-narmstrong-sm8550-upstream-remoteproc-v1-0-104c34cb3b91@linaro.org/ [2] https://lore.kernel.org/all/20221116103146.2556846-1-abel.vesa@linaro.org/ [3] https://lore.kernel.org/all/20221114-narmstrong-sm8550-upstream-mpss_dsm-v1-0-158dc2bb6e96@linaro.org/ --- Abel Vesa (1): arm64: dts: qcom: sm8550: Add interconnect path to SCM node Neil Armstrong (2): arm64: dts: qcom: sm8550: add adsp, cdsp & mdss support nodes arm64: dts: qcom: sm8550-mtp: enable adsp, cdsp & mdss arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 18 ++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 338 ++++++++++++++++++++++++++++++++ 2 files changed, 356 insertions(+) --- base-commit: a237afe452d9079aa024e465642b4cde0a04c7ff change-id: 20221115-topic-sm8550-upstream-dts-remoteproc-5285d7018e39 Best regards, -
sent/topic/sm8550/upstream/qce-v17cd71fee · ·
crypto: qcom-qce: add support for SM8550 This adds the necessary bindings and driver changes to enable the Qualcomm Crypto engine on the SM8550 SoC. Dependencies: - https://lore.kernel.org/all/20220920114051.1116441-1-bhupesh.sharma@linaro.org/ -- To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Vinod Koul <vkoul@kernel.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Herbert Xu <herbert@gondor.apana.org.au> To: "David S. Miller" <davem@davemloft.net> To: Bhupesh Sharma <bhupesh.sharma@linaro.org> To: Thara Gopinath <thara.gopinath@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: dmaengine@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Abel Vesa (1): dt-bindings: dma: qcom,bam-dma: Add 'interconnects' and 'interconnect-names' Neil Armstrong (3): dt-bindings: qcom-qce: document clocks and clock-names as optional dt-bindings: qcom-qce: document sm8550 compatible crypto: qce: core: Add new compatibles for SM8550 Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 3 +-- Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 8 ++++++++ drivers/crypto/qce/core.c | 1 + 3 files changed, 10 insertions(+), 2 deletions(-) --- base-commit: 8931ecbe1f2017471608e262dd2914ce376155a4 change-id: 20221114-narmstrong-sm8550-upstream-qce-ed3135413002 Best regards, -
sent/topic/sm8550/upstream/i2c-master-hub-v1ac37b23b · ·
soc: qcom: add support for the I2C Master Hub The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. The I2C Master Hub only supports a variant of the I2C serial engine with: - a separate "core" clock - no DMA support - non discoverable fixed FIFO size Since DMA isn't supported, the wrapper doesn't need the Master AHB clock and the iommus property neither. This patchset adds the bindings changes to the QUPv3 wrapper and I2C serial element bindings to reflect the different resources requirements. In order to reuse the QUPv3 wrapper and I2C serial element driver support, the I2C Master Hub requirements are expressed in new desc structs passed as device match data. To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-i2c@vger.kernel.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Neil Armstrong (6): dt-bindings: qcom: geni-se: document I2C Master Hub wrapper variant dt-bindings: i2c: qcom-geni: document I2C Master Hub serial I2C engine soc: qcom: geni-se: add desc struct to specify clocks from device match data soc: qcom: geni-se: add support for I2C Master Hub wrapper variant i2c: qcom-geni: add desc struct to prepare support for I2C Master Hub variant i2c: qcom-geni: add support for I2C Master Hub variant .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 61 ++++++++++++++++---- .../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 43 +++++++++++--- drivers/i2c/busses/i2c-qcom-geni.c | 58 ++++++++++++++++++- drivers/soc/qcom/qcom-geni-se.c | 67 +++++++++++++++++----- 4 files changed, 192 insertions(+), 37 deletions(-) --- base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3 change-id: 20221114-narmstrong-sm8550-upstream-i2c-master-hub-44a7fb19475e Best regards, -
sent/topic/sm8550/upstream/remoteproc-v1f20fcb17 · ·
remoteproc: qcom_q6v5_pas: add support for SM8550 adsp, cdsp & mpss This patchsets adds support for the aDSP, cDSP and MPSS found in the SM8550 SoC. The aDSP, cDSP and MPSS boot process on SM8550 now requires a secondary "Devicetree" firmware to be passed along the main Firmware, and the cDSP a new power domain named "NSP". In order to satisfy the load & authentication order required by the SM8550 SoC, the following is implemented: - "Devicetree" firmware request & load in dedicated memory - Q6V5 prepare - Power Domain & Clocks enable - "Devicetree" firmware authentication - Main firmware load in dedicated memory - Main firmware authentication - Q6V5 startup - "Devicetree" firmware metadata release - Main metadata release When booting older platforms, the "Devicetree" steps would be bypassed and the load & authentication order would still be valid. To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Mathieu Poirier <mathieu.poirier@linaro.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Manivannan Sadhasivam <mani@kernel.org> To: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> To: Amol Maheshwari <amahesh@qti.qualcomm.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-remoteproc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Abel Vesa (1): dt-bindings: misc: qcom,fastrpc: increase allowed iommus entries Neil Armstrong (3): dt-bindings: remoteproc: qcom: adsp: document sm8550 adsp, cdsp & mpss compatible remoteproc: qcom_q6v5_pas: add support for dtb co-firmware loading remoteproc: qcom_q6v5_pas: add sm8550 adsp, cdsp & mpss compatible & data .../devicetree/bindings/misc/qcom,fastrpc.yaml | 2 +- .../devicetree/bindings/remoteproc/qcom,adsp.yaml | 60 ++++++- drivers/remoteproc/qcom_q6v5_pas.c | 199 +++++++++++++++++++-- 3 files changed, 246 insertions(+), 15 deletions(-) --- base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3 change-id: 20221114-narmstrong-sm8550-upstream-remoteproc-804f3fbb34bf Best regards, -
sent/topic/sm8550/upstream/mpss_dsm-v1a358e7cd · ·
soc: qcom: Add support for Qualcomm Modem Processing SubSystem DSM memory The Qualcomm SM8550 SoC Modem Processing SubSystem requires that a memory region named DSM should be shared with the Application Processor SubSystem. This adds bindings for this MPSS DSM memory and driver implementation to share this memory region with the Modem Processing SubSystem. To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Frank Rowand <frowand.list@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Neil Armstrong (2): dt-bindings: reserved-memory: document Qualcomm MPSS DSM memory soc: qcom: add MDSS DSM memory driver .../reserved-memory/qcom,mpss-dsm-mem.yaml | 37 +++++++++ drivers/of/platform.c | 1 + drivers/soc/qcom/Kconfig | 10 +++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/mpss_dsm_mem.c | 95 ++++++++++++++++++++++ 5 files changed, 144 insertions(+) --- base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3 change-id: 20221114-narmstrong-sm8550-upstream-mpss_dsm-21c438c65f9b Best regards, -
sent/topic/sm8550/upstream/sdhci-v1eb89c089 · ·
dt-bindings: mmc: sdhci-msm: Document the SM8550 compatible From: Abel Vesa <abel.vesa@linaro.org> Document the compatible for SDHCI on SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- To: Ulf Hansson <ulf.hansson@linaro.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Bhupesh Sharma <bhupesh.sharma@linaro.org> Cc: linux-mmc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Abel Vesa <abel.vesa@linaro.org> --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index fc8a6b345d97..f0b7e6d0ecbf 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -49,6 +49,7 @@ properties: - qcom,sm8150-sdhci - qcom,sm8250-sdhci - qcom,sm8450-sdhci + - qcom,sm8550-sdhci - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 reg: --- base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3 change-id: 20221114-narmstrong-sm8550-upstream-sdhci-1ae5ac4924e5 Best regards, -
sent/topic/sm8550/upstream/bwmon-v11c7f63d3 · ·
dt-bindings: interconnect: qcom-bwmon: document SM8550 compatibles This documents the compatibles used to describe the Bandwidth Monitors present on the SM8550 platform. A BWMON v4 IP monitors the CPU bandwidth, and a v5 does the LLCC bandwidth monitoring. This is described this by adding "llcc" and "cpu" into the compatible strings to differentiate the BWMON IPs. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Georgi Djakov <djakov@kernel.org> To: Rob Herring <robh+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index be29e0b80995..00b635662697 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -26,8 +26,13 @@ properties: - enum: - qcom,sc7280-cpu-bwmon - qcom,sdm845-bwmon + - qcom,sm8550-cpu-bwmon - const: qcom,msm8998-bwmon - const: qcom,msm8998-bwmon # BWMON v4 + - items: + - enum: + - qcom,sm8550-llcc-bwmon + - const: qcom,sc7280-llcc-bwmon - const: qcom,sc7280-llcc-bwmon # BWMON v5 - const: qcom,sdm845-llcc-bwmon # BWMON v5 --- base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3 change-id: 20221114-narmstrong-sm8550-upstream-bwmon-a7c6227fab6d Best regards, -
sent/topic/sm8550/upstream/gpi-v1f218f8cc · ·
dt-bindings: dma: qcom: gpi: add compatible for sm8550 The Qualcomm SM8550 uses GPI DMA for its GENI interface. Add a compatible string for it in the documentation by using the SM6350 as fallback. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Vinod Koul <vkoul@kernel.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: dmaengine@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index e7ba1c47a88e..99c224836bfd 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -29,6 +29,7 @@ properties: - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma + - qcom,sm8550-gpi-dma - const: qcom,sm6350-gpi-dma - items: - enum: --- base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3 change-id: 20221114-narmstrong-sm8550-upstream-gpi-59edc9c3bbef Best regards, -
sent/topic/sm8550/upstream/spmi-v1d1278947 · ·
qcom: add support for SPMI PMICs found on SM8550 platforms The SM8550 based platforms sports a bunch of new PMICs: - pm8550 - pm8550b - pm8550ve - pm8550vs - pmk8550 - pmr735d - pm8010 With GPIO support on: - pm8550 - pm8550b - pm8550ve - pm8550vs - pmk8550 - pmr735d This documents bindings for those SPMI PMIC and adds compatible in the PMIC pinctrl driver for GPIO support. To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Lee Jones <lee@kernel.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Stephen Boyd <sboyd@kernel.org> To: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-gpio@vger.kernel.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Neil Armstrong (7): dt-bindings: mfd: qcom,spmi-pmic: document pm8550, pm8550b, pm8550ve, pm8550vs & pmk8550 dt-bindings: mfd: qcom,spmi-pmic: document pm8010 dt-bindings: mfd: qcom,spmi-pmic: document pmr735d dt-bindings: pinctrl: qcom,pmic-gpio: document pm8550, pm8550b, pm8550ve, pm8550vs & pmk8550 dt-bindings: pinctrl: qcom,pmic-gpio: document pmr735d pinctrl: qcom: spmi-gpio: add support for pm8550 gpio control pinctrl: qcom: spmi-gpio: add support for pmr735d gpio control .../devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 7 +++++++ .../devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 18 ++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 6 ++++++ 3 files changed, 31 insertions(+) --- base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3 change-id: 20221114-narmstrong-sm8550-upstream-spmi-d2c999ec5dc1 Best regards, -
sent/topic/sm8550/upstream/tsens-v190e78ac4 · ·
dt-bindings: thermal: qcom-tsens: Add compatible for sm8550 The Qualcomm SM8550 platform has three instances of the tsens block, add a compatible for these instances. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Amit Kucheria <amitk@kernel.org> To: Thara Gopinath <thara.gopinath@gmail.com> To: "Rafael J. Wysocki" <rafael@kernel.org> To: Daniel Lezcano <daniel.lezcano@linaro.org> To: Zhang Rui <rui.zhang@intel.com> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index f0bd4b979e28..09dbd96d380e 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -58,6 +58,7 @@ properties: - qcom,sm8250-tsens - qcom,sm8350-tsens - qcom,sm8450-tsens + - qcom,sm8550-tsens - const: qcom,tsens-v2 - description: v2 of TSENS with combined interrupt --- base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3 change-id: 20221114-narmstrong-sm8550-upstream-tsens-dfaec218c321 Best regards, -
sent/mdm9615-pinctrl-yaml-v452571f54 · ·
arm: qcom: mdm9615: second round of bindings and DT fixes This is a second round of bindings & DT fixes for the MDM9615 platform. This second round focuses on less trivial changes like pinctrl & regulators bindings, the remaining work will mainly be fixing the qcom,kpss-timer/qcom,msm-timer situation and add bindings for qcom,lcc-mdm9615, qcom,kpss-gcc & swir,mangoh-iotport-spi. Dependencies: None To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Liam Girdwood <lgirdwood@gmail.com> To: Mark Brown <broonie@kernel.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Lee Jones <lee@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v4: - Removed applied patches - Removed "-ipc" from bindings file name and removed IPC from title & description - Added the review tags from v3 after file renaming & title/description change, after Lee's acceptation - Link to v3: https://lore.kernel.org/r/20221005-mdm9615-pinctrl-yaml-v3-0-e5e045644971@linaro.org Changes in v3: - Path 1: Removed from serie because applied - Path 2: None - Path 3: Added reviewed-by tag - Path 4: Fixed dt-schema title and added unevaluatedProperties - Path 5: Various schema fixes, uses same naming as other dt-schema for qcom regulators - New patch added changing regulators names of msm8660 to conform to bindings - Link to v2: https://lore.kernel.org/r/20221005-mdm9615-pinctrl-yaml-v2-0-639fe67a04be@linaro.org Changes in v2: - Rebased on v6.1-rc1 - Patch 1: Fixed bindings and aligned with Krysztof's series - Patch 2: Rewrote patch title and added reviewed-by tag - Patch 3: Added reviewed-by tag - Patch 4: Moved to end, added support for (regulators|-regulators) sudnode - Patch 5: Fixed schema description and added missing unevaluatedProperties in patternProperties - Patch 6: Dropped & squashed with patch 4 - Link to v1: https://lore.kernel.org/r/20221005-mdm9615-pinctrl-yaml-v1-0-0cbc006e2a30@linaro.org --- Neil Armstrong (2): dt-bindings: regulators: convert non-smd RPM Regulators bindings to dt-schema dt-bindings: soc: qcom: convert non-smd RPM bindings to dt-schema Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 283 --------------------- .../bindings/regulator/qcom,rpm-regulator.yaml | 128 ++++++++++ .../devicetree/bindings/soc/qcom/qcom,rpm.yaml | 101 ++++++++ 3 files changed, 229 insertions(+), 283 deletions(-) --- base-commit: 19d64985796125c5e3820c3db995c5df6d13d6dc change-id: 20221005-mdm9615-pinctrl-yaml-13f5c18a4d3a Best regards, -
sent/mdm9615-sx1509q-yaml-v3c28bcc85 · ·
dt-bindings: pinctrl: convert semtech,sx150xq bindings to dt-schema This converts the Semtech SX150Xq bindings to dt-schemas, add necessary bindings documentation to cover all differences between HW variants and current bindings usage. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> --- To: Linus Walleij <linus.walleij@linaro.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- Changes in v3: - Resent with missing To: Linus Walleij - Link to v2: https://lore.kernel.org/r/20221005-mdm9615-sx1509q-yaml-v2-0-a4a5b8eecc7b@linaro.org Changes in v2: - fixed rob comments - added rob's Reviewed-by - Link to v1: https://lore.kernel.org/r/20221005-mdm9615-sx1509q-yaml-v1-0-0c26649b637c@linaro.org --- .../devicetree/bindings/pinctrl/pinctrl-sx150x.txt | 72 ------- .../bindings/pinctrl/semtech,sx1501q.yaml | 208 +++++++++++++++++++++ 2 files changed, 208 insertions(+), 72 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt deleted file mode 100644 index 4023bad2fe39..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt +++ /dev/null @@ -1,72 +0,0 @@ -SEMTECH SX150x GPIO expander bindings - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -Required properties: -- compatible: should be one of : - "semtech,sx1501q", - "semtech,sx1502q", - "semtech,sx1503q", - "semtech,sx1504q", - "semtech,sx1505q", - "semtech,sx1506q", - "semtech,sx1507q", - "semtech,sx1508q", - "semtech,sx1509q". - -- reg: The I2C slave address for this device. - -- #gpio-cells: Should be 2. The first cell is the GPIO number and the - second cell is used to specify optional parameters: - bit 0: polarity (0: normal, 1: inverted) - -- gpio-controller: Marks the device as a GPIO controller. - -Optional properties : -- interrupts: Interrupt specifier for the controllers interrupt. - -- interrupt-controller: Marks the device as a interrupt controller. - -- semtech,probe-reset: Will trigger a reset of the GPIO expander on probe, - only for sx1507q, sx1508q and sx1509q - -The GPIO expander can optionally be used as an interrupt controller, in -which case it uses the default two cell specifier. - -Required properties for pin configuration sub-nodes: - - pins: List of pins to which the configuration applies. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - bias-disable: disable any pin bias, except the OSCIO pin - - bias-pull-up: pull up the pin, except the OSCIO pin - - bias-pull-down: pull down the pin, except the OSCIO pin - - bias-pull-pin-default: use pin-default pull state, except the OSCIO pin - - drive-push-pull: drive actively high and low - - drive-open-drain: drive with open drain only for sx1507q, sx1508q and sx1509q and except the OSCIO pin - - output-low: set the pin to output mode with low level - - output-high: set the pin to output mode with high level - -Example: - - i2c0gpio-expander@20{ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1506q"; - reg = <0x20>; - interrupt-parent = <&gpio_1>; - interrupts = <16 0>; - - gpio-controller; - interrupt-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_cfg_pins>; - - gpio1_cfg_pins: gpio1-cfg { - pins = "gpio1"; - bias-pull-up; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml new file mode 100644 index 000000000000..df429a396ba3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml @@ -0,0 +1,208 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/semtech,sx1501q.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Semtech SX150x GPIO expander + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + enum: + - semtech,sx1501q + - semtech,sx1502q + - semtech,sx1503q + - semtech,sx1504q + - semtech,sx1505q + - semtech,sx1506q + - semtech,sx1507q + - semtech,sx1508q + - semtech,sx1509q + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + '#gpio-cells': + const: 2 + + gpio-controller: true + + semtech,probe-reset: + description: Will trigger a reset of the GPIO expander on probe + type: boolean + +patternProperties: + '-cfg$': + type: object + properties: + pins: true + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + bias-pull-pin-default: true + drive-push-pull: true + output-low: true + output-high: true + drive-open-drain: true + + required: + - pins + + allOf: + - $ref: "pincfg-node.yaml#" + - $ref: "pinmux-node.yaml#" + - if: + properties: + pins: + contains: + const: oscio + then: + properties: + bias-disable: false + bias-pull-up: false + bias-pull-down: false + bias-pull-pin-default: false + drive-open-drain: false + + additionalProperties: false + +required: + - compatible + - reg + - '#gpio-cells' + - gpio-controller + +allOf: + - $ref: "pinctrl.yaml#" + - if: + not: + properties: + compatible: + contains: + enum: + - semtech,sx1507q + - semtech,sx1508q + - semtech,sx1509q + then: + properties: + semtech,probe-reset: false + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1501q + - semtech,sx1504q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^gpio[0-3]$' + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1502q + - semtech,sx1505q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^gpio[0-7]$' + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1503q + - semtech,sx1506q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^gpio[0-15]$' + - if: + properties: + compatible: + contains: + const: semtech,sx1507q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(oscio|gpio[0-3])$' + - if: + properties: + compatible: + contains: + const: semtech,sx1508q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(oscio|gpio[0-7])$' + - if: + properties: + compatible: + contains: + const: semtech,sx1509q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(oscio|gpio[0-15])$' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c@1000 { + reg = <0x1000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl@20 { + compatible = "semtech,sx1501q"; + reg = <0x20>; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + interrupt-controller; + + gpio1-cfg { + pins = "gpio1"; + bias-pull-up; + }; + }; + }; --- base-commit: 4fe89d07dcc2804c8b562f6c7896a45643d34b2f change-id: 20221005-mdm9615-sx1509q-yaml-7cfabf896fff Best regards, -
sent/mdm9615/dt-schema-fixes-v5e352e1d4 · ·
arm: qcom: mdm9615: first round of bindings and DT fixes This is a first round of trivial bindings & DT fixes for the MDM9615 platform. This first round focuses on trivial changes, the remaining work will mainly be .txt to .yaml transition of old qcom pmic & co device bindings. To: Andy Gross <agross@kernel.org> To: Bjorn Andersson <andersson@kernel.org> To: Konrad Dybcio <konrad.dybcio@somainline.org> To: Alessandro Zummo <a.zummo@towertech.it> To: Alexandre Belloni <alexandre.belloni@bootlin.com> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Satya Priya <quic_c_skakit@quicinc.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-rtc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Dependencies: None Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v5: - Removed applied patches - Link to v4: https://lore.kernel.org/r/20220928-mdm9615-dt-schema-fixes-v4-0-dac2dfaac703@linaro.org Changes in v4: - patch 1: None - patch 2: None - patch 3: None - patch 4: None - patch 5: Added reviewed-by tag - patch 6: Fix descriptions, Added reviewed-by tags - patch 7: None - patch 8: None - patch 9: Added acked-by tag - patch 10: None - patch 11: None - Link to v3: https://lore.kernel.org/r/20220928-mdm9615-dt-schema-fixes-v3-0-531da552c354@linaro.org Changes in v3: - Rebased on v6.1-rc1 - patch 1: Added reviewed-by tag - patch 2: Fixes typo in commit msg and added precision about why MIT was selected - patch 3: Added reviewed-by tag - patch 4: None - patch 5: Drop second example node - patch 6: Drop Andy, fix interrupts desc and fix example indentation - patch 7: Fix commit msg wrap & add reviewed-by tag - patch 8: Reword commit msg & add reviewed-by tag - patch 9: Reword commit msg & add reviewed-by tag - patch 10: None - patch 11: Added reviewed-by tag - Link to v2: https://lore.kernel.org/r/20220928-mdm9615-dt-schema-fixes-v2-0-87fbeb4ae053@linaro.org Changes in v2: - patch 1: switch to move from swir.txt to qcom.yaml - patch 2: use MIT licence instead of X11 licence - patch 3: move reg after compatible - patch 4: added Krzysztof's review - patch 5: split into 5 changes: - document qcom,pm8921 as fallback of qcom,pm8018 - convert qcom,pm8921-pwrkey to dt-schema - document qcom,pm8921-rtc as fallback of qcom,pm8018-rtc - drop unused PM8018 compatible - drop unused pm8018 RTC compatible - patch 6: None - patch 7: Reworded commit log based on Dmitry's wording on similar patches - Link to v1: https://lore.kernel.org/r/20220928-mdm9615-dt-schema-fixes-v1-0-b6e63a7df1e8@linaro.org --- Neil Armstrong (2): dt-bindings: rtc: qcom-pm8xxx: document qcom,pm8921-rtc as fallback of qcom,pm8018-rtc rtc: pm8xxx: drop unused pm8018 compatible .../devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml | 16 ++++++++++------ drivers/rtc/rtc-pm8xxx.c | 1 - 2 files changed, 10 insertions(+), 7 deletions(-) --- base-commit: 9abf2313adc1ca1b6180c508c25f22f9395cc780 change-id: 20220928-mdm9615-dt-schema-fixes-66d4d0ccb7c7 Best regards, -
sent/spicc-burst-delay-fix-v29d2ab984 · ·
spi: meson-spicc: fix do_div build error on non-arm64 This fixes : error: passing argument 1 of '__div64_32' from incompatible pointer type By passing an uint64_t as first variable to do_div(). Reported-by: kernel test robot <lkp@intel.com> Fixes: 04694e50020b ("spi: meson-spicc: move wait completion in driver to take bursts delay in account") Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- To: Mark Brown <broonie@kernel.org> To: Kevin Hilman <khilman@baylibre.com> To: Jerome Brunet <jbrunet@baylibre.com> To: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: linux-spi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- Changes in v2: - Added Martin's Acked-by - Added Reported-by: kernel test robot - Added To: Mark Brown - Link to v1: https://lore.kernel.org/r/20221027-b4-spicc-burst-delay-fix-v1-0-5a6e9a88e54c@linaro.org --- drivers/spi/spi-meson-spicc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 52bffab18329..1b4195c54ee2 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -387,7 +387,7 @@ static int meson_spicc_transfer_one(struct spi_master *master, struct spi_transfer *xfer) { struct meson_spicc_device *spicc = spi_master_get_devdata(master); - unsigned long timeout; + uint64_t timeout; /* Store current transfer */ spicc->xfer = xfer; --- base-commit: 574f97ab96d6b153407161746bc127564e998b4f change-id: 20221027-b4-spicc-burst-delay-fix-a03004454876 Best regards, -
sent/odroid-go-ultra-initial-v11cc9073d · ·
arm64: amlogic: add initial Odroid Go Ultra DTS This adds initial support for the Hardkernel Odroid Go Ultra. The Odroid Go Ultra is a portable gaming device with the following characteristics: - Amlogic S922X SoC - RK817 & RK818 PMICs - 2GiB LPDDR4 - On board 16GiB eMMC - Micro SD Card slot - 5inch 854×480 MIPI-DSI TFT LCD - Earphone stereo jack, 0.5Watt 8Ω Mono speaker - Li-Polymer 3.7V/4000mAh Battery - USB-A 2.0 Host Connector - x16 GPIO Input Buttons - 2x ADC Analog Joysticks - USB-C Port for USB2 Device and Charging The following are not yet handled: - Battery RK818 Gauge and Charging - Earphone stereo jack detect - 5inch 854×480 MIPI-DSI TFT LCD This adds: - Poweroff bindings - Poweroff driver - Device bindings - Initial device DT This serie depends on: - https://lore.kernel.org/all/20221025-rk808-multi-v2-0-d292d51ada81@linaro.org/ To: Sebastian Reichel <sre@kernel.org> To: Rob Herring <robh+dt@kernel.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> To: Kevin Hilman <khilman@baylibre.com> To: Jerome Brunet <jbrunet@baylibre.com> To: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: linux-pm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Neil Armstrong (4): dt-bindings: reset: document Odroid Go Ultra power-off power: reset: add Odroid Go Ultra poweroff driver dt-bindings: amlogic: document Odroid Go Ultra compatible arm64: dts: amlogic: add initial Odroid Go Ultra DTS Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + .../reset/hardkernel,odroid-go-ultra-poweroff.yaml | 42 ++ arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/meson-g12b-odroid-go-ultra.dts | 730 +++++++++++++++++++++ drivers/power/reset/Kconfig | 7 + drivers/power/reset/Makefile | 1 + drivers/power/reset/odroid-go-ultra-poweroff.c | 122 ++++ 7 files changed, 904 insertions(+) --- base-commit: 247f34f7b80357943234f93f247a1ae6b6c3a740 change-id: 20221031-b4-odroid-go-ultra-initial-5e65cde5e23a Best regards,