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  1. Apr 11, 2018
  3. Apr 07, 2018
  5. Apr 06, 2018
    • Tobin C. Harding's avatar
      MAINTAINERS: Update LEAKING_ADDRESSES · e875d33d
      Tobin C. Harding authored 
      
MAINTAINERS is out of date for leaking_addresses.pl. There is now a tree on
kernel.org for development of this script.  We have a second maintainer now,
thanks Tycho.  Development of this scripts was started on kernel-hardening
mailing list so let's keep it there.

Update maintainer details; Add mailing list, kernel.org hosted tree, and second
maintainer.

Signed-off-by: default avatarTobin C. Harding <me@tobin.cc>
      e875d33d
  7. Apr 05, 2018
  9. Apr 04, 2018
  11. Apr 03, 2018
    • Lorenzo Pieralisi's avatar
      MAINTAINERS: Add missing /drivers/pci/cadence directory entry · 86df1073
      Lorenzo Pieralisi authored 
      
Commit 37dddf14 ("PCI: cadence: Add EndPoint Controller driver for
Cadence PCIe controller") created the /drivers/pci/cadence directory to
keep in a single place Cadence host and endpoint controller drivers.

Since code in /drivers/pci/cadence falls within the PCI native host
bridge and endpoint controllers mainteinance remit, that maintainer
entry should have been updated too by adding the /drivers/pci/cadence
directory to it but it actually was not.

Update the MAINTAINERS entry accordingly, fixing the omission.

Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Alan Douglas <adouglas@cadence.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
      86df1073
  13. Apr 02, 2018
  15. Mar 30, 2018
  17. Mar 29, 2018
  19. Mar 28, 2018
  21. Mar 26, 2018
  23. Mar 23, 2018
  25. Mar 22, 2018
  27. Mar 21, 2018
  29. Mar 20, 2018
  31. Mar 17, 2018
  33. Mar 16, 2018
    • Jesper Nilsson's avatar
      CRIS: Drop support for the CRIS port · c690eddc
      Jesper Nilsson authored 
      
The port was added back in 2000 so it's no longer even a good source
of inspiration for newer ports (if it ever was)

The last SoC (ARTPEC-3) with a CRIS main CPU was launched in 2008.

Coupled with time and working developer board hardware being
in low supply, it's time to drop the port from Linux.

So long and thanks for all the fish!

Signed-off-by: default avatarJesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      c690eddc
    • Arnd Bergmann's avatar
      arch: remove tile port · bb9d8126
      Arnd Bergmann authored 
      The Tile architecture port was added by Chris Metcalf in 2010, and
maintained until early 2018 when he orphaned it due to his departure
from Mellanox, and nobody else stepped up to maintain it. The product
line is still around in the form of the BlueField SoC, but no longer
uses the Tile architecture.

There are also still products for sale with Tile-GX SoCs, notably the
Mikrotik CCR router family. The products all use old (linux-3.3) kernels
with lots of patches and won't be upgraded by their manufacturers. There
have been efforts to port both OpenWRT and Debian to these, but both
projects have stalled and are very unlikely to be continued in the future.

Given that we are reasonably sure that nobody is still using the port
with an upstream kernel any more, it seems better to remove it now while
the port is in a good shape than to let it bitrot for a few years first.

Cc: Chris Metcalf <chris.d.metcalf@gmail.com>
Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Link: http://www.mellanox.com/page/npu_multicore_overview
Link: https://jenkins.debian.net/view/rebootstrap/job/rebootstrap_tilegx_gcc7/


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      bb9d8126
    • Arnd Bergmann's avatar
      arch: remove blackfin port · 4ba66a97
      Arnd Bergmann authored 
      The Analog Devices Blackfin port was added in 2007 and was rather
active for a while, but all work on it has come to a standstill
over time, as Analog have changed their product line-up.

Aaron Wu confirmed that the architecture port is no longer relevant,
and multiple people suggested removing blackfin independently because
of some of its oddities like a non-working SMP port, and the amount of
duplication between the chip variants, which cause extra work when
doing cross-architecture changes.

Link: https://docs.blackfin.uclinux.org/


Acked-by: default avatarAaron Wu <Aaron.Wu@analog.com>
Acked-by: default avatarBryan Wu <cooloney@gmail.com>
Cc: Steven Miao <realmz6@gmail.com>
Cc: Mike Frysinger <vapier@chromium.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      4ba66a97
  35. Mar 15, 2018