misc: mnh: Update PRQ DDR Driver baseline

* Created function mnh_ddr_pi_int_status_bit
to read PI int status bits.
* Add precautionary check of PI status being done
during initialization.
* Created function mnh_ddr_write_clk_from_fsp
instead of longer macro for WRITE_CLK_FROM_FSP.
Added precaution of freezing PLL during writes.
* Override power-on defaults of clock div fields to avoid
known issue (already corrected in FSP settings in regconfig)
to avoid div by 1.
* DDR interrupt status spans two registers.
Modified mnh_ddr_clr_int_status to change order of
clearing lower bits first it as sometimes immediately reading it
after still has bit 35 set which is the logical OR of all
bits in the status.
* Removed orphan / unused function mnh_ddr_disable_odt
* Added iso_n gpio reference to ddr driver internal state.
* Modified register pull/backup during suspend
and register restoration during resume to reflect that
boot (FSP0) is not included in the PHYs internal
copies thus FSP1 corresponds to PHY freq. index 0.
* Removed debug reads of mode register 4
* Move resume register overrides to mnh_ddr_po_init
after init done is received.
* Remove suspend_fsp from mnh_ddr_internal_state and
macros to read and write it.
* only switch freq. on suspend if needed.
* added misc. timing instrumentation

Bug: 111652429
Bug: 118765019
Change-Id: Id8aa5120ca022b499188e24f8b0abd16a392aacc
Signed-off-by: Anthony Loeppert <anthony.loeppert@intel.com>
Signed-off-by: Cheng Gu <gucheng@google.com>