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  1. Apr 23, 2019
    • Linus Walleij's avatar
      clocksource/drivers/ixp4xx: Add driver · 13e0b405
      Linus Walleij authored
      
      This adds a new slightly rewritten timer driver for the
      Intel IXP4xx clocksource, clockevent and delay timer.
      
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      13e0b405
    • Linus Walleij's avatar
      gpio: ixp4xx: Add driver for the IXP4xx GPIO · 813e7d36
      Linus Walleij authored
      
      This adds a driver for the IXP4xx GPIO block found in
      the Intel XScale IXP4xx systems.
      
      The GPIO part of this block is pretty straight-forward and
      just uses the generic MMIO GPIO library.
      
      The irqchip side of this driver is hierarchical where
      the main irqchip will receive a processed level trigger
      in response to the edge detector of the GPIO block,
      so for this reason the v2 version of the irqdomain API
      is used (as well as in the parent IXP4xx irqchip) and
      masking, unmasking and setting up the type on IRQ
      happens on several levels.
      
      Currently this GPIO controller will grab the parent
      irqdomain using a special function, but as the platform
      move toward device tree probing, this will not be needed:
      we can just look up the parent irqdomain from the device
      tree.
      
      Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      813e7d36
  2. Apr 19, 2019
    • Linus Walleij's avatar
      irqchip: Add driver for IXP4xx · 5b978c10
      Linus Walleij authored
      
      The IXP4xx (arch/arm/mach-ixp4xx) is an old Intel XScale
      platform that has very wide deployment and use.
      
      As part of modernizing the platform, we need to implement a
      proper irqchip in the irqchip subsystem.
      
      The IXP4xx irqchip is tightly jotted together with the GPIO
      controller, and whereas in the past we would deal with this
      complex logic by adding necessarily different code, we can
      nowadays modernize it using a hierarchical irqchip.
      
      The actual IXP4 irqchip is a simple active low level IRQ
      controller, whereas the GPIO functionality resides in a
      different memory area and adds edge trigger support for
      the interrupts.
      
      The interrupts from GPIO lines 0..12 are 1:1 mapped to
      a fixed set of hardware IRQs on this IRQchip, so we
      expect the child GPIO interrupt controller to go in and
      allocate descriptors for these interrupts.
      
      For the other interrupts, as we do not yet have DT
      support for this platform, we create a linear irqdomain
      and then go in and allocate the IRQs that the legacy
      boards use. This code will be removed on the DT probe
      path when we add DT support to the platform.
      
      We add some translation code for supporting DT
      translations for the fwnodes, but we leave most of that
      for later.
      
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      5b978c10
    • Linus Walleij's avatar
      ARM: ixp4xx: Add myself as maintainer · 64534e06
      Linus Walleij authored
      
      I am working on the platform right now so might as well
      maintain it for a bit.
      
      Suggested-by: default avatarKrzysztof Hałasa <khalasa@piap.pl>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      64534e06
  3. Mar 15, 2019
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