- Jul 29, 2022
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Nick Hawkins authored
Create documentation for the hpe,gxp-spifi binding to support access to the SPI parts Signed-off-by:
Nick Hawkins <nick.hawkins@hpe.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220728161459.7738-3-nick.hawkins@hpe.com Signed-off-by:
Mark Brown <broonie@kernel.org>
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Nick Hawkins authored
The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash and bios part. Signed-off-by:
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- Jul 26, 2022
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Krzysztof authoredThe spi-cpha and spi-cpol properties are device specific and should be accepted only if device really needs them. Drop them from common spi-peripheral-props.yaml schema, mention in few panel drivers which use them and include instead in the SPI controller bindings. The controller bindings will provide CPHA/CPOL type validation and one place for description. Each device schema must list the properties if they are applicable. Suggested-by:
Jonathan Cameron <jic23@kernel.org> Suggested-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- Jul 25, 2022
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Martin Sperl authored
BCM2711 shares an interrupt betweem 5 SPI interfaces (0, 3, 4, 5 & 6). Another interrupt is shared between SPI1, SPI2 and UART1, which also affects BCM2835/6/7. Acting on an interrupt intended for another interface ought to be harmless (although potentially inefficient), but it can cause this driver to crash - presumably because some critical state is not ready. Add a test to the spi-bcm2835 interrupt service routine that interrupts are enabled on this interface to avoid the crash and improve efficiency. Signed-off-by:
Martin Sperl <kernel@martin.sperl.org> Link: https://github.com/raspberrypi/linux/issues/5048 Suggested-by: https://github.com/boe-pi Co-developed-by:
Phil Elwell <phil@raspberrypi.com> Signed-off-by:
Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20220719105305.3076354-1-mkl@pengutronix.de Signed-off-by:
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- Jul 22, 2022
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Krzysztof authored
Example DTS mixed two with four-space indentation. Preferred is four spaces, for readability. Signed-off-by:
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- Jul 20, 2022
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Mark Brown authored
Merge series from Tomer Maimon <tmaimon77@gmail.com>: This patch set adds Arbel NPCM8XX Flash Interface Unit (FIU) support to FIU NPCM driver and modify direct read dummy configuration. NPCM8XX FIU supports four controllers. The NPCM FIU driver tested on NPCM845 evaluation board.
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Krzysztof authored
Recent Qualcomm Geni SPI nodes, e.g. on SM8450, come also with three interconnects. This fixes dtbs_check warnings like: sm8450-qrd.dtb: spi@a98000: interconnects: [[46, 1, 0, 46, 4, 0], [47, 2, 0, 48, 12, 0], [49, 1, 0, 50, 1, 0]] is too long sm8450-qrd.dtb: spi@a98000: interconnect-names: ['qup-core', 'qup-config', 'qup-memory'] is too long Fixes: 5bdcae1f ("spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema") Signed-off-by:
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Tomer Maimon authored
Adding FIU NPCM8XX support to NPCM FIU driver. NPCM8XX FIU supports four controllers. As part of adding NPCM8XX support: - Add NPCM8XX specific compatible string. - Using an internal burst configuration register instead of a GCR register. - Support FIU1 controller. Signed-off-by:
Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220718081146.256070-4-tmaimon77@gmail.com Signed-off-by:
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Tomer Maimon authored
Add a compatible string and description for Nuvoton BMC NPCM845 FIU. Signed-off-by:
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Tomer Maimon authored
Modify NPCM BMC FIU direct read dummy configuration that according spi-mem direct read function. Signed-off-by:
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- Jul 18, 2022
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Claudiu Beznea authored
Remove #ifdef CONFIG_PM, #ifdef CONFIG_PM_SLEEP and use SYSTEM_SLEEP_PM_OPS() and RUNTIME_PM_OPS() macros instead which allows getting also rid of __maybe_unused in the code. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220718071052.1707858-1-claudiu.beznea@microchip.com Signed-off-by:
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Johnson Wang authored
This commit adds dt-binding documentation of spi bus for MediaTek MT8188 SoC platform. Signed-off-by:
Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220715120114.4243-1-johnson.wang@mediatek.com Signed-off-by:
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Allen-KH Cheng authored
The spi-mtk-nor controller of mt8173, mt8186 and mt8192 have their DT data. They don't use mt8173 as fallback. Using the fallback of mt8186 to enables the controllers to support mt8188. Not all of spi-mtk-nor controller need interrupt property, so we don't mark interrupt as required. Signed-off-by:
Allen-KH Cheng <allen-kh.cheng@mediatek.com> Link: https://lore.kernel.org/r/20220715115443.4154-1-allen-kh.cheng@mediatek.com Signed-off-by:
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- Jul 14, 2022
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Sergiu Moga authored
Convert SPI DT binding for Atmel/Microchip SoCs to json-schema. Signed-off-by:
Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by:
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- Jul 13, 2022
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Mark Brown authored
Merge series from nandhini.srikandan@intel.com <nandhini.srikandan@intel.com>: This patch enables support for DW SPI on Intel Thunder Bay. This patch set also enables master mode for latest Designware SPI versions. The driver is tested on Keem Bay and Thunder Bay evaluation board.
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Mark Brown authored
Merge series from Yang Yingliang <yangyingliang@huawei.com>: Patch #1 fix a UAF in mchp_corespi_remove(). Patch #2 and #3 some cleanups to simpify code.
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Yang Yingliang authored
After calling spi_unregister_master(), the refcount of master will be decrease to 0, and it will be freed in spi_controller_release(), the device data also will be freed, so it will lead a UAF when using 'tspi'. To fix this, get the master before unregister and put it when finish using it. Fixes: 26c86341 ("spi: tegra20-slink: Don't use resource-managed spi_register helper") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220713094024.1508869-1-yangyingliang@huawei.com Signed-off-by:
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Yang Yingliang authored
This reverts commit 59ebbe40 ("spi: simplify devm_spi_register_controller"). If devm_add_action() fails in devm_add_action_or_reset(), devm_spi_unregister() will be called, it decreases the refcount of 'ctlr->dev' to 0, then it will cause uaf in the drivers that calling spi_put_controller() in error path. Fixes: 59ebbe40 ("spi: simplify devm_spi_register_controller") Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220712135504.1055688-1-yangyingliang@huawei.com Signed-off-by:
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Yang Yingliang authored
Switch to use dev_err_probe() to simpify error path. Signed-off-by:
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Yang Yingliang authored
Switch to use devm_spi_alloc_master() to simpify error path. Signed-off-by:
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Yang Yingliang authored
When using devm_spi_register_master(), the unregister function will be called in devres_release_all() which is called after ->remove(), so remove spi_unregister_master() andspi_master_put(). Fixes: 9ac8d176 ("spi: add support for microchip fpga spi controllers") Signed-off-by:
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Nandhini Srikandan authored
Add support for Intel Thunder Bay SPI controller, which uses DesignWare DWC_ssi core and also add common init function for both Keem Bay and Thunder Bay. Signed-off-by:
Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by:
Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-5-nandhini.srikandan@intel.com Signed-off-by:
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Nandhini Srikandan authored
Add support to select the controller mode as master mode by setting Bit 31 of CTRLR0 register. This feature is supported for controller versions above v1.02. Signed-off-by:
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Nandhini Srikandan authored
Add documentation for SPI controller in Intel Thunder Bay SoC. Signed-off-by:
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Nandhini Srikandan authored
Add the missing underscore in IP version macro to avoid compilation issue. The macro is used for IP version comparison in the current patchset. Fixes: 2cc8d922 ("spi: dw: Introduce Synopsys IP-core versions interface") Signed-off-by:
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- Jul 11, 2022
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Andy Shevchenko authored
The acpi_spi_add_resource() is never called with ctrl == NULL and index == -1. The only caller already performs the check. Hence remove the duplication from the acpi_spi_add_resource(). Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220709000709.35622-2-andriy.shevchenko@linux.intel.com Signed-off-by:
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Andy Shevchenko authored
Since acpi_spi_device_alloc() has been designed to return an error pointer we may now properly propagate error codes to the caller of it. It helps debugging a lot. Signed-off-by:
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Andy Shevchenko authored
If the controller is not available, it might be in the future and we would like to re-probe the peripheral again. For that purpose return deferred probe. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=215993 Fixes: 87e59b36 ("spi: Support selection of the index of the ACPI Spi Resource before alloc") Signed-off-by:
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- Jul 06, 2022
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Mark Brown authored
Merge series from Cristian Ciocaltea <cristian.ciocaltea@collabora.com>: This patch series addresses an issue in the spi-amd driver and, while there, performs some additional cleanups, like simplifying the error handling in the probe function and removing an unused struct member. For improving code readability, it also adds some kernel-doc comments.
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Cristian Ciocaltea authored
Provide documentation comments in the kernel-doc format for enum amd_spi_versions and struct amd_spi. Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-6-cristian.ciocaltea@collabora.com Signed-off-by:
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Cristian Ciocaltea authored
The io_base_addr member of struct amd_spi is not referenced anywhere in the driver implementation and there is no indication that it could be used in the future, hence drop it. Signed-off-by:
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Cristian Ciocaltea authored
Simplify the error handling in probe function by switching from dev_err() to dev_err_probe(). Signed-off-by:
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Cristian Ciocaltea authored
Make use of the devm variant of spi_alloc_master() in order to cleanup and simplify the error handling in the probe function by getting rid of the goto statements. Signed-off-by:
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Cristian Ciocaltea authored
Enabling the SPI CS35L41 audio codec driver for Steam Deck [1] revealed a problem with the current AMD SPI controller driver implementation, consisting of an unrecoverable system hang. The issue can be prevented if we ensure the max transfer size and the max message size do not exceed the FIFO buffer size. According to the implementation of the downstream driver, the AMD SPI controller is not able to handle more than 70 bytes per transfer, which corresponds to the size of the FIFO buffer. Hence, let's fix this by setting the SPI limits mentioned above. [1] https://lore.kernel.org/r/20220621213819.262537-1-cristian.ciocaltea@collabora.com Reported-by:
Anastasios Vacharakis <vacharakis@o2mail.de> Fixes: bbb336f3 ("spi: spi-amd: Add AMD SPI controller driver support") Signed-off-by:
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- Jul 04, 2022
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Krzysztof authored
During the conversion the bindings lost list of required properties. Fixes: c58db2ab ("spi: convert Xilinx Zynq UltraScale+ MPSoC GQSPI bindings to YAML") Signed-off-by:
Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20220704130618.199231-2-krzysztof.kozlowski@linaro.org Signed-off-by:
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Krzysztof authored
During the conversion the bindings lost list of required properties. Fixes: aa796868 ("spi: convert Cadence SPI bindings to YAML") Signed-off-by:
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- Jul 01, 2022
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Conor Dooley authored
Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the Canaan k210 is wired up for a width of 4. Quoting Serge: The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. /endquote As such, drop the restriction on only supporting a bus width of 1. Link: https://lore.kernel.org/all/20220620205654.g7fyipwytbww5757@mobilestation/ Signed-off-by:Niklas Cassel <niklas.cassel@wdc.com> Link: https://lore.kernel.org/r/20220629184343.3438856-5-mail@conchuod.ie Signed-off-by:
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- Jun 30, 2022
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Mark Brown authored
Merge series from David Jander <david@protonic.nl>: This series fixes some coding style issues. No functional change.
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David Jander authored
Reported-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220629142519.3985486-4-david@protonic.nl Signed-off-by:
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David Jander authored
Capitalize first word in comment where appropriate and add parentheses to function names. Reported-by:
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