- Mar 15, 2023
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Mani Sadhasivam authored
Both Rishabh and Sai have left Qualcomm, and there is no evidence of them maintaining with a new identity. So their entry needs to be removed. Listed Bjorn as the interim maintainer until someone volunteers to maintain this binding. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230314080443.64635-2-manivannan.sadhasivam@linaro.org
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- Dec 05, 2022
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Abel Vesa authoredAdd LLCC compatible for SM8550 SoC. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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- Jul 21, 2022
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Slark Xiao authored
Fix typo in the comment Signed-off-by:
Slark Xiao <slark_xiao@163.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220721011746.19663-1-slark_xiao@163.com
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- May 04, 2022
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Bjorn Andersson authored
Add compatibles for the SC8180X and SC8280XP platforms to the existing LLCC binding. Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by:
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- Mar 10, 2022
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Anup Patel authored
The RISC-V CPU idle states will be described in under the /cpus/idle-states DT node in the same way as ARM CPU idle states. This patch adds common bindings documentation for both ARM and RISC-V idle states. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Guo Ren <guoren@kernel.org> Signed-off-by:
Palmer Dabbelt <palmer@rivosinc.com>
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- Feb 11, 2022
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Sai Prakash Ranjan authored
Add LLCC compatible for SM8450 SoC. Cc: Rob Herring <robh@kernel.org> Signed-off-by:
Sai Prakash Ranjan <quic_saipraka@quicinc.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Tested-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Sai Prakash Ranjan authored
Add LLCC compatible for SM8350 SoC. Cc: Rob Herring <robh@kernel.org> Signed-off-by:
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- Dec 21, 2021
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Luca Weiss authored
Newer SoCs like SM6350 or SM8250 don't provide an interrupt for LLCC. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Acked-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Add LLCC compatible for SM6350 SoC. Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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- Jun 16, 2021
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Add the dt-binding compatible in the SPM AVS Wrapper 2 (SAW2) for the MSM8226 SoC platform. Acked-by:
Bartosz Dudziak <bartosz.dudziak@snejp.pl> Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20210612205335.9730-2-bartosz.dudziak@snejp.pl
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- Mar 12, 2021
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Sai Prakash Ranjan authored
Add LLCC compatible for SC7280 SoC. Acked-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/f3b32d437d7c1165a74ceec2cd52ff56b496e5a3.1614244789.git.saiprakash.ranjan@codeaurora.org Signed-off-by:
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- Dec 28, 2020
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Mani Sadhasivam authored
Add LLCC compatible for SM8250 SoC. Signed-off-by:
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- Nov 20, 2020
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Souradeep Chowdhury authored
Add LLCC compatible for SM8150 SoC. Acked-by:
Souradeep Chowdhury <schowdhu@codeaurora.org> Link: https://lore.kernel.org/r/141e7cf03932859243edec83451c04c655ba640b.1601452132.git.schowdhu@codeaurora.org Signed-off-by:
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- Mar 31, 2020
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Rob Herring authored
Setting 'additionalProperties: false' is frequently omitted, but is important in order to check that there aren't extra undocumented properties in a binding. Ideally, we'd just add this automatically and make this the default, but there's some cases where it doesn't work. For example, if a common schema is referenced, then properties in the common schema aren't part of what's considered for 'additionalProperties'. Also, sometimes there are bus specific properties such as 'spi-max-frequency' that go into bus child nodes, but aren't defined in the child node's schema. So let's stick with the json-schema defined default and add 'additionalProperties: false' where needed. This will be a continual review comment and game of wack-a-mole. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Acked-by:
Mark Brown <broonie@kernel.org> Acked-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by:
Alexandru Ardelean <alexandru.ardelean@analog.com> Reviewed-by:
Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Stephen Boyd <sboyd@kernel.org> # clock Acked-by:
Lee Jones <lee.jones@linaro.org>
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- Feb 24, 2020
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Mauro Carvalho Chehab authored
Several DT references got broken due to txt->yaml conversion. Those are auto-fixed by running: scripts/documentation-file-ref-check --fix Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Acked-by:
Andrew Jeffery <andrew@aj.id.au> Reviewed-by:
Dan Murphy <dmurphy@ti.com> Reviewed-by:
Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by:
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- Dec 11, 2019
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Sai Prakash Ranjan authored
DT schema checks for the node name 'cache-controller' and enforces that there has to be a cache-level associated with it. But LLCC is a system cache and does not have a cache-level property and hence the dt binding check fails. So let us rename the LLCC cache-controller to system-cache-controller which is the proper description and also makes the schema happy. Acked-by:
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- Oct 21, 2019
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Sai Prakash Ranjan authored
Add LLCC compatible for SC7180 SoC. Reviewed-by:
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Sai Prakash Ranjan authored
Convert LLCC bindings to DT schema format using json-schema. Reviewed-by:
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- Oct 17, 2018
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Stephen Boyd authored
The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. Documenting the bindings here. Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Sricharan R <sricharan@codeaurora.org> Tested-by:
Craig Tatlor <ctatlor97@gmail.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- Sep 13, 2018
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Venkata Narendra Kumar Gutta authored
Add reg-names and interrupts for LLCC documentation and the usage examples. llcc broadcast base is added in addition to llcc base, which is used for llcc broadcast writes. Signed-off-by:
Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Reviewed-by:
Andy Gross <andy.gross@linaro.org>
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- Jul 21, 2018
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Rishabh Bhatnagar authored
Documentation for last level cache controller device tree bindings, client bindings usage examples. Signed-off-by:
Channagoud Kadabi <ckadabi@codeaurora.org> Signed-off-by:
Rishabh Bhatnagar <rishabhb@codeaurora.org> Reviewed-by:
Evan Green <evgreen@chromium.org> Reviewed-by:
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- Apr 27, 2018
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Rob Herring authored
Bindings are supposed to be organized by device class/function. Move bindings for various timers to timer/ binding directory. Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by:
Thierry Reding <thierry.reding@gmail.com> Signed-off-by:
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- Apr 22, 2015
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Mathieu Olivari authored
The watchdog has been reworked to use the same DT node as the timer. This change is updating the device tree doc accordingly. Signed-off-by:
Mathieu Olivari <mathieu@codeaurora.org> Acked-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Wim Van Sebroeck <wim@iguana.be>
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- Apr 03, 2015
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Lina Iyer authored
Document cpuidle states of QCOM cpus. In addition to arm-idle-state compatible string, the ARM idle state definition must define one of the following compatible strings - "qcom,idle-state-ret", "qcom,idle-state-spc", "qcom,idle-state-pc", The compatibles helps the SPM platform driver to use the correct idle function when the index to the idle state is passed to the platform driver. Signed-off-by:
Lina Iyer <lina.iyer@linaro.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Lina Iyer authored
Update qcom,saw2 node bindings with compatible strings to identify nodes that provides cpuidle functionality for a particular SoC. Remove unused compatible strings. Update examples for different SAW nodes. Signed-off-by:
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- Jan 28, 2015
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Masanari Iida authored
This patch fix multiple words such as "the the" and "which which" in Documentation/devicetree. Signed-off-by:
Masanari Iida <standby24x7@gmail.com> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- Feb 11, 2014
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Stephen Boyd authored
The saw2 binding describes the SPM/AVS wrapper hardware used to control the regulator supplying voltage to the Krait CPUs. Cc: <devicetree@vger.kernel.org> Signed-off-by:
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Stephen Boyd authored
The kpss acc binding describes the clock, reset, and power domain controller for a Krait CPU. Cc: <devicetree@vger.kernel.org> Signed-off-by:
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- Mar 25, 2013
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David Brown authored
The SSBI bus is exclusive to the Qualcomm MSM targets, and all SoCs using it will be using device tree. Convert this driver to indentify with device tree. This makes the bus probing a good bit simpler, since the attaching of child nodes can be represented directly in the devicetree, rather than having to be inferred by name. Signed-off-by:
David Brown <davidb@codeaurora.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- Mar 22, 2013
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Stephen Boyd authored
The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by:
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- Sep 13, 2012
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Stephen Boyd authored
Add support to setup the MSM timer via information obtained from the devicetree. Signed-off-by:
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