Change-Id: I4016950ae01c9f58d2dd38d7e819f419e701f080

There is a new programming sequence on Kona, the register of
QDSS_QDSS_CS_QDSSCSR_USBFLSHCTRL should be configured after
programming TMC ETR registers. This changes use new programming
sequence to enable etr to bam. Add sysfs interface in CSR to let
user space change usb flush period.

Change-Id: I0cee7db746106fd0318d01a92682f185cb31ad97
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>

Correct the VA SWR_ADC routings in atoll wcd937x variant
to fix the headset SVA detection issue.

Change-Id: I25de822b25ddd8bc08cffadfd884cd80163787f8
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>

The current code uses the rq->cpu_capacity_orig while sorting
the min/mid/max CPUs while rebuilding the scheduler domains. This
rq->cpu_capacity_orig is subjected to changed when the scaling max
frequency is clipped for that CPU's frequency domain. Since we don't
recompute the min/mid/max CPUs when the capacity is changed, the
sorting becomes incorrect later when the frequency limits are lifted.

The task CPU selection algorithm depends heavily on min/mid/max CPUs
and changing them on the fly results in incorrect task placement.
Hence use the true capacity of CPUs while sorting the min/mid/max
CPUs. This means that the sorting gets changed only when CPUs are
hotplugged out, otherwise these reflect the correct topology
all the time.

The max_cpu_capacity struct in root domain also maintains the
max CPU and its capacity. Since we now use true capacity, there
is no need to compute this on the fly. So move this evaluation from
the periodic load balancer to the scheduler domain rebuilding.

The rq->cpu_capacity_orig is still subjected to change upon frequency
or thermal limits. So we still identify the cases where tasks not
fitting on the max/mid CPUs when the capacity is reduced.

Change-Id: I42735accd079b2ece1eb58d1ebcf322d454e33a2
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>

Ratelimit the logs indicating invalid packet status fields.
Support DL Frag rule status opcode. The logs introduces
delay during modem ssr.

Change-Id: I92ebf8776dd0e81653c968985818124cbe539d5f
Signed-off-by: Akshay Pandit <pandit@codeaurora.org>

Whenever sensor driver event notification happens, of thermal
framework notifies all thermal zones associated to that sensor for
thermal re-evaluation. In this case, thermal zones whose trips are
not violated are also forced to re-evaluate.

Check if any trip of a thermal zone is violated, then notify that
zone for thermal re-evaluation and ignore other thermal zones
whose trips are not violated.

Change-Id: I3bed9738edc4c1ef4cd3b9748c2b50256941dc7d
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>

Changing CMA alignment to 4 from dafult value 8 to
effective use of cma pool for multiple clients.

Change-Id: Ifd8f64daf0033087bcd7d10e84773e06c507169e
Signed-off-by: Vishwanath Raju K <vishk@codeaurora.org>

For SSR, add a 200ms delay after powering off QCA6x90 device.

Change-Id: I7ae05675228cf2e3d5a004a2e5ce8d6bae752415
Signed-off-by: jiad <jiad@codeaurora.org>

While GDSP is turned off, it requires bandwidth to be voted to
save some information to memory. This change is to move bandwidth
unvoting after turning off GDSC.

Change-Id: Ie7c30eb0a1aee58aa835133f0336f0164492d732
Signed-off-by: Da Hoon Pyun <dpyun@codeaurora.org>

The mailbox controller implemented in NPU works as a bridge
between ipcc_mproc mailbox controller and its clients. It is
required because npu driver needs to control when IPCC irq can
be sent to NPUQ6.

Change-Id: I998c66c55ce0d959a3fe0dc382d2bbb9ccbe8e84
Signed-off-by: Da Hoon Pyun <dpyun@codeaurora.org>

This change restricts disabling of Flow control and interrupts
only for HSUART case. Fundamentally Console usecase need not
have flow control need as part of baud rate change. Also do not
touch interrupts for console usecase as it results into imbalance
of the irq.

Change-Id: Ic6964f5b18c8dc4223a2b2a68f16af33359b3e6e
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>

Update skin thermal zone mitigation thresholds and cooling device
levels for ATOLL based on latest recommendation.

Change-Id: I43bb655e7783bc1db1844fbc96c5b6cad55e67bd
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>

Update chain0 and chain1 regulator voltage level
for atoll.

Change-Id: I2b81900e2c9680934357c60f615ece2156592f23
Signed-off-by: Sandeep Singh <sandsing@codeaurora.org>

Currently the USB3 primary controller has core clk rate for HS as
10 MHz. This leads to throughput degradation. Update this rate to
100 MHz for better throughput.

Change-Id: I5db9e6f5987b49702c6e8c935ef1735569b459e6
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>

There is a possibility of race condition between
drain_apps_data and process_apps_data for flushing
the apps data buffer to mux, Which can cause flushing
buffer twice and can lead to use-after-free issue.
The patch adds checks for buffer flush status before
using the same buffer for processing apps data.

Change-Id: I2cfe67304e73bcb4004884b986ac2bec44b29ba1
Signed-off-by: Hardik Arya <harya@codeaurora.org>

Add device tree files to support sdx ipc driver for LE-CPE V1/V2
on sdxprairie target.

Change-Id: I71e5be73f4f223d83e6043fc19c072fb5a0d523b
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>