- Sep 06, 2019
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Alexander Shishkin authored
commit 9c78255f upstream. This adds support for the Trace Hub in Tiger Lake PCH. Signed-off-by:
Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org # v4.14+ Link: https://lore.kernel.org/r/20190821074955.3925-5-alexander.shishkin@linux.intel.com Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Alexander Shishkin authored
commit 164eb56e upstream. Add support for the Trace Hub in another Lewisburg PCH. Signed-off-by:
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- Jul 26, 2019
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Alexander Shishkin authored
commit 4aa5aed2 upstream. This adds Ice Lake NNPI support to the Intel(R) Trace Hub. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20190621161930.60785-5-alexander.shishkin@linux.intel.com Signed-off-by:
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- May 10, 2019
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Alexander Shishkin authored
commit e60e9a4b upstream. This adds support for Intel TH on Comet Lake. Signed-off-by:
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- Sep 18, 2018
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Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Ice Lake PCH. Signed-off-by:
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- Mar 28, 2018
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Alexander Shishkin authored
This adds SPDX GPL-2.0 header to the Trace Hub driver and removes the GPLv2 boilerplate text. Signed-off-by:
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- Sep 22, 2017
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Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Lewisburg PCH. Signed-off-by:
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Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Cedar Fork PCH. Signed-off-by:
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- Aug 25, 2017
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Alexander Shishkin authored
On some devices (TH 2.x devices at the moment), the internal time counter is initially not synchronized to the global crystal clock, so the time stamps it produces will not be useful. In this case, the driver needs to force the time counter resync. This applies the workaround to relevant devices. Signed-off-by: -
Alexander Shishkin authored
Allow attaching miscellaneous quirk information to devices as drvdata. Signed-off-by: -
Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-LP. Signed-off-by: -
Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-H. Signed-off-by: -
Alexander Shishkin authored
The driver forgets to enable bus mastering for the PCI device. Fix this. Signed-off-by:
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- Mar 15, 2017
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Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Gemini Lake SOC. Signed-off-by: -
Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Denverton SOC. Signed-off-by:
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- Jul 14, 2016
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Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Kaby Lake PCH-H. Signed-off-by:
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- Apr 19, 2016
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Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Broxton-M SOC. Signed-off-by:
Laurent Fert <laurent.fert@intel.com>
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- Feb 20, 2016
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Alexander Shishkin authored
Already during the subdevice initialization time, devices will need to reference Intel TH controller descriptor structure. This patch moves setting the drvdata from the pci glue to intel_th core, before subdevices are populated. Signed-off-by:
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- Feb 08, 2016
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Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Broxton SOC. Signed-off-by:
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Alexander Shishkin authored
This adds Intel(R) Trace Hub PCI ID for Apollo Lake SOC. Signed-off-by:
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- Oct 04, 2015
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Alexander Shishkin authored
This patch adds basic support for PCI-based Intel TH devices. It requests 2 bars (configuration registers for the subdevices and STH channel MMIO region) and calls into Intel TH core code to create the bus with subdevices etc. Signed-off-by:
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