- Jan 06, 2021
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Internal buffers required for v6 decoder are different than encoder so add a separate list for the decoder. bod: fixed up if/else, removed redundant bool Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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- Internal buffers required by v6 are different than v4, add new list of internal buffers for v6. - Fix the macro definitions of internal buffer list for v6. Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Do not toggle the WRAPPER_A9SS_SW_RESET on 6xx. Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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When in vcodec_control_v4() on the 4xx path we select between one of two vcodec cores to toggle power control bits. In 6xx there is only one core which offsets the relevant control registers to a slightly different address. This patch accounts for the address offset for 6xx silicon. Co-developed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch takes the downstream AXI halt routine and applies it when IS_V6() is true. bod: Converted to readl_poll_timeout() Converted LPI update timeout to dev_dbg. In practice this register never appears to update with the value 0x07. Discussing with contacts in qcom video team, this toggle only pertains to low-power mode. Keeping the write for the sake of fidelity with downstream. Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Co-developed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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- Jan 05, 2021
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Bryan O'Donoghue authored
In various places in the venus codebase we have if (IS_V4()) which takes the code down paths for 4xx silicon. This logic is broadly applicable to 6xx silicon also. In this patch we add IS_V6() to various IS_V4() decision locations. Co-developed-by:
Dikshita Agarwal <dikshita@qti.qualcomm.com> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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- Dec 29, 2020
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Bryan O'Donoghue authored
This commit make a pm_ops structure for the V6 silicon. As an initial pass it copies the v4 pm_ops structure and callbacks. For the most part the logic for both IP blocks looks the same however there are a few differences we will need to capture for v6. Existing v4 operations should cover most of it. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
On 6xx we should read wrapper cpu status from the wrapper TZ register set. Co-developed-by:
Jonathan Marek <jonathan@marek.ca> Co-developed-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This commit adds 6xx specific interrupt support, some register offsets and bitmasks differ from 4xx, which we account for in this commit. [bod: Added commit log. Moved register definition into commit] Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Co-developed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch adds a 6xx specific boot logic. The goal is to share as much code as possible between 3xx, 4xx and 6xx silicon. We need to do a different write to WRAPPER_INTR_MASK with an additional write to CPU_CS_H2XSOFTINTEN_V6 and CPU_CS_X2RPMh_V6. The other writes are the same for 6xx and non-6xx silicon albeit at different absolute relative locations to the base of the venus address space. Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
This commit points the IO base registers 6xx offsets when probing for 6xx hardware. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
6xx silicon needs to access registers from a AON base address range. This commit defines the necessary variable for later use. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
6xx silicon needs to access registers from a wrapper trust-zone base address range. This commit defines the necessary variable for later use. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
An upcoming silicon change places a number of existing blocks within the Venus at different relative offsets to the base address of IO region. In order to handle this difference this patch changes the address offsets of the registers to function as offsets relative to the relevant sub-block of registers within the IO region not the base address of the IO region. As a result of this change venus_readl() and venus_writel() are deleted. Co-developed-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
New silicon means that the pre-determined offsets we have been using in this driver no longer hold. Existing blocks of registers can exist at different offsets relative to the IO base address. This commit adds a routine to assign the IO base hooks a subsequent commit will convert from absolute to relative addressing. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This commit defines debug bridge LPI status and control registers. Co-developed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This commit defines a 6xx wrapper tz base address and associated status register. Co-developed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This commit adds offset and register definition for the AON block. This block is necessary to gate the AXI bus on 6xx. Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Co-developed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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The wrapper power registers are not related to a specific codec core but rather to just one core on 6xx and reside at a different offset to 4xx. This commit adds the necessary register offset definitions for 6xx. Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Co-developed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Add X2 RPMh registers and definitions from the downstream example. Co-developed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This commit defines a range of new base addresses for already defined blocks. - CPU_BASE_V6 - CPU_CS_BASE_V6 - CPU_IC_BASE_V6 - WRAPPER_BASE_V6 The base addresses of the blocks are slightly different for 6xx but, aside from that are layout and bit compatible. New 6xx specific block addresses will be added in separate commits. Co-developed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
This commit converts the addresses specified in hfi_venus_io.h to values that are relative to the respective block base addresses - for example VBIF or WRAPPER. This is a necessary precursor to adding in support for 6xx silicon where 6xx locates blocks such as WRAPPER at different bases in what is otherwise a broadly register compatible way. Co-developed-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
This commit adds the macro helper IS_V6() which will be used to differentiate iris2/v6 silicon from previous versions. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Vote for min clk frequency for core clks during prepare and enable clocks at boot sequence. Without this the controller clock runs at very low value (9.6MHz) which is not sufficient to boot venus. Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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The Venus driver has to control two reset signals related to gcc video_axi0 and videocc mvs0c for v6. Add it. Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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On the sm8250 in order to get the gcc_video_axi0_clk up and running we need to set video-mem NOC bandwidth to non-zero. In this case the maximum bandwidth value is set to the value given in downstream 15000000 kbps. bod: - Did some debug around this, set the avg_bw = 0, retained peak_bw = 15000000 - Made into a standalone patch - Added commit log and SOB Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
Adds an sm8250 compatible binding to the venus core. Co-developed-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
Enable the building of the sm8250 video clock controller by default. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
Add DT entries for the sm8250 venus encoder/decoder. Co-developed-by:
Jonathan Marek <jonathan@marek.ca> Co-developed-by:
Dikshita Agarwal <dikshita@qti.qualcomm.com> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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- Dec 23, 2020
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This commit adds the videocc DTS node for sm8250. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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- Dec 21, 2020
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Bryan O'Donoghue authored
This commit adds a regulator supply hook to mmcx-reg Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
This patch adds the missing video_cc_mvs0_div_clk entry to videocc-sm8250. There has been some debate about whether or not this entry is required to be specified and interacted with specifically. Looking at downstream this clock is brought out in this way so, to err on the side of caution we should replicate in upstream. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
This patch adds the missing video_cc_mvs0_div_clk_src entry to videocc-sm8250. There has been some debate about whether or not this entry is required to be specified and interacted with specifically. Looking at downstream this clock is brought out in this way so, to err on the side of caution we should replicate in upstream. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Now when everything is in place wire up buffer requirements from hfi platform buffers to the buffer requirements helper. Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Handle progressive/interlaced bitstream event by similar way as bit depth. Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Wire up hfi platform codec and capabilities instead of getting them from firmware. Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Add a new file for hfi platform buffer size and count calculations for v6. Co-developed-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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From Venus v6 and beyond the buffer size and count have to be calculated in the v4l2 driver instead of getting them from firmware. Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Add new hfi platform file with capabilities of hfi v6. Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Starting from v6 we have one more hfi property which will be needed to calculate buffer sizes/count for particular codec and session type. Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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