Skip to content
Snippets Groups Projects
  1. Sep 27, 2023
  2. Sep 22, 2023
  3. Sep 21, 2023
  4. Sep 18, 2023
  5. Sep 13, 2023
  6. Sep 08, 2023
  7. Sep 05, 2023
  8. Sep 04, 2023
  9. Sep 02, 2023
  10. Sep 01, 2023
    • Lad Prabhakar's avatar
      cache: Add L2 cache management for Andes AX45MP RISC-V core · d34599bc
      Lad Prabhakar authored
      I/O Coherence Port (IOCP) provides an AXI interface for connecting
      external non-caching masters, such as DMA controllers. The accesses
      from IOCP are coherent with D-Caches and L2 Cache.
      
      IOCP is a specification option and is disabled on the Renesas RZ/Five
      SoC due to this reason IP blocks using DMA will fail.
      
      The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
      block that allows dynamic adjustment of memory attributes in the runtime.
      It contains a configurable amount of PMA entries implemented as CSR
      registers to control the attributes of memory locations in interest.
      Below are the memory attributes supported:
      * Device, Non-bufferable
      * Device, bufferable
      * Memory, Non-cacheable, Non-bufferable
      * Memory, Non-cacheable, Bufferable
      * Memory, Write-back, No-allocate
      * Memory, Write-back, Read-allocate
      * Memory, Write-back, Write-allocate
      * Memory, Write-back, Read and Write-allocate
      
      More info about PMA (section 10.3):
      Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
      
      
      
      As a workaround for SoCs with IOCP disabled CMO needs to be handled by
      software. Firstly OpenSBI configures the memory region as
      "Memory, Non-cacheable, Bufferable" and passes this region as a global
      shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
      allocations happen from this region and synchronization callbacks are
      implemented to synchronize when doing DMA transactions.
      
      Example PMA region passes as a DT node from OpenSBI:
          reserved-memory {
              #address-cells = <2>;
              #size-cells = <2>;
              ranges;
      
              pma_resv0@58000000 {
                  compatible = "shared-dma-pool";
                  reg = <0x0 0x58000000 0x0 0x08000000>;
                  no-map;
                  linux,dma-default;
              };
          };
      
      Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
      Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
      Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
      Link: https://lore.kernel.org/r/20230818135723.80612-6-prabhakar.mahadev-lad.rj@bp.renesas.com
      
      
      Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
  11. Aug 29, 2023
  12. Aug 27, 2023
  13. Aug 25, 2023
  14. Aug 23, 2023
  15. Aug 22, 2023
  16. Aug 21, 2023
  17. Aug 20, 2023
  18. Aug 18, 2023
  19. Aug 17, 2023
  20. Aug 16, 2023
Loading